Circuit means for cyclically monitoring and indicating the condition of a function

ABSTRACT

A stepping chain-type digitizer for monitoring the condition of a function and for converting the condition into true and false conditions of the steps of the chain whereby any change of the monitored condition produces a change in the condition of the steps. The steps of the stepping chain are utilized to control inhibitor gates placed in the stages of the normally free-running ring counter. Any stage of the ring counter controlled by a step in a selected condition remains in the &#39;&#39;&#39;&#39;on&#39;&#39;&#39;&#39; position after the counter advances to turn it &#39;&#39;&#39;&#39;on,&#39;&#39;&#39;&#39; and thereby stops any further advance of the ring counter. The stage of the ring counter which remains locked in the &#39;&#39;&#39;&#39;on&#39;&#39;&#39;&#39; position provides the indication of the condition of the monitored function.

United States Patent Inventor Russel T. Stebbins Mountain View, Calif.

App]. No. 72,897

Filed Sept. 16, 1970 Patented Dec. 7, 1971 Assignee ltek CorporationLexington, Mass.

Continuation of application Ser. No. 690,647, Dec. 14, 1967, nowabandoned. This application Sept. 16, 1970, Ser. No. 72,897

CIRCUIT MEANS FOR CYCLICALLY MONITORING AND INDICATING THE CONDITION OFA FUNCTION 13 Claims, 3 Drawing Figs.

Primary ExaminerDonald D, Forrer Assistant Examiner--R. C. WoodbridgeAttorneysl-larvey G. Lowhurst, Homer 0. Blair, Robert L.

Nathans and Lester S. Goldberg ABSTRACT: A stepping chain-type digitizerfor monitoring the condition of a function and for converting thecondition into true and false conditions of the steps of the chainwhereby any change of the monitored condition produces a change in thecondition of the steps, The steps of the stepping chain are utilized tocontrol inhibitor gates placed in the stages of the normallyfree-running ring counter. Any stage of the ring counter controlled by astep in a selected condition remains in the on" position after thecounter advances to turn it on, and thereby stops any further advance ofthe ring counter. The stage of the ring counter which remains locked inthe on" position provides the indication of the condition of themonitored function.

/0 F L I l l l STAGE STAGE STAGE STAGE STAGE 1 2 3 4 5 ,L s

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21; {20 i 3 /4 Y I I I RESET 2 i a 4 j. d fixg MEANS ms ER MONITOREDPATENTED DEC 7197! SHEET 1 BF 2 4 N D E MGR m m Ell WBN F O M 1 6 6 m 52 I -l R Il -P- 3 3 m Ill- D w m w 8 UN SA v EE M RM INVENTOR RUSSELL TSTEBBINS VOLTAGE DIGITIZER STAGE RANGES Fig-2 PATENTED BEE 71971 SHEET 20F 2 nvvmrok RUSSELLT. STEBBINS ATll/PNEY CIRCUIT MEANSFOR CYCLICALLYMONITORING AND IN DICATING THE CONDITION OF A FUNCTION This is acontinuation of Ser. No. 690,647 filed Dec. 14,

BACKGROUND OF THE INVENTION 1. Field of the Invention This inventionrelates to apparatus for cyclically monitoring and continuouslyindicating the condition of a function, and, more particularly, to amonitoring and indicating system which continually and cyclicallyprovides an indication of a digitized quantity.

It is often highly desirable to derive an indication whether a certainfunction is above, below, or within one or more preselected rangeswithout actually undertaking a numerical evaluation of the quantitybeing measured. For example, when checking the reflectivity of a surfaceduring a manufacturing process, the actual reflectivity is easilymeasured by determining the current originated by a photoelectric sensorexposed to light reflected from the surface, or, the voltage across aresistor in the photoelectric cell circuit. If the total range ofreflectivity is expressed in some arbitrary units ranging from one tofive, and only surfaces having a reflectivity between three and four aredetermined as acceptable, the apparatus of this invention is ideallysuited for providing an indication of an acceptable reflectivity withoutactually obtaining the numerical value of the reflectivity. In otherwords, this device is eminently suitable for automatically andcontinually testing, measuring, or otherwise monitoring a specifiedcondition of a function which may be the reflectivity of a surface asdescribed above or any other function such as resistivity, cleanliness,hardness, inductivity, to mention only a few.

2. Description of the Prior Art Heretofore, a number of circuits havebeen in use for monitoring the condition of a function, most of whichare of the metering type providing an indication of the actual conditionof the function. One such device is the voltmeter.

Each of these devices, whatever may be their construction, are deficientwith respect to one or more of the following. They do not provide asimple indication of an acceptable range of conditions of the functionwhich is cyclically repeated at a readily selectable repetitionfrequency, which is efficient, reliable, inexpensive, substantiallyfoolproof, and readily adaptable to automatic processing.

It is, therefore, an object of the present invention to provide acircuit by which a cyclically repeating indication of the condition of afunction being monitored can be obtained.

It is a further object of the present invention to provide a circuit formonitoring a function and for providing an indication on the basis ofwhich it is immediately determinable that the function falls within orwithout certain preselected limits.

it is still another object of the invention to digitize the condition ofa function by means of a stepping chain and to monitor the condition ofeach step to thereby determine the condition of the function.

It is also an object of the invention to convert an analog signal to adigital signal and to cyclically and continuously monitor the digitalsignal to determine the condition of an analog function.

It is a further object of the invention to utilize a normallyfree-running ring counter to monitor a stepping chain which in turn isset to reflect the present condition of an analog functron.

SUMMARY OF THE INVENTION In accordance with one embodiment of thepresent invention, the condition of a function such as the magnitude ofa voltage, is digitized by means of a stepping chain or digitizer havinga preselected number of steps or output stages. The output stages of thedigitizer are either at a first potential signifying a true condition,or at a second potential signifying a false condition, depending on theamplitude of the voltage being monitored. Each time the amplitude of thevoltage being monitored increases by one digit, the stepping chain stepsforward by one step and the output stage corresponding to this stepchanges either from true to false, or from false to true.

The output stages of the digitizer are continually being monitored by anormally free-running ring counter having anumber of stages whichcorresponds to the number of steps of the stepping chain. Each stage ofthe ring counter monitors a different step of the digitizer, andincludes a locking means which is responsive to the condition of themonitored step, and which will lock the counter stage and thereby thering counter from further advance when the monitored step is in aselected (or true) condition.-

There is also provided a cycle signal which unblocks the locked stage ofthe ring counter, and which resets the ring counter to start a new cyclewith stage one." During the new cycle, the ring counter will again stopits advance when reaching a stage receiving a true signal from thedigitizer, The stage at which the ring counter stops thereby provides anindication of the condition of the function being monitored which iscyclically repeated so that the indication of the function beingmonitored determined by the ring counter is constantly checked.

Further objects and advantages of the present invention will becomeapparent to those skilled in the art to which the invention pertains asthe ensuing description proceeds.

The features of novelty that are considered characteristic of thisinvention are set forth with particularity in the appended claims. Theorganization and method of operation of the invention itself will bestbe understood from the following description when read in connectionwith the accompanying drawing in which BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1 is a schematic block diagram of a cyclically monitoring andindicating circuit constructed in accordance with the present invention;

FIG. 2 is a truth table for the digitizer shown in FIG. 1; and

FIG. 3 is a schematic circuit diagram of an exemplary embodiment of acyclically monitoring and indicating circuit incorporating the presentinvention.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to FIG. 1 of thedrawing, there is shown a free-running ring counter 10 comprised of fivestages which are identified as Stages 1 to Stage 5. There is furtherprovided a digitizer 12, which may take the form of a stepping chain,for monitoring a function 14 connected thereto by means of conductor 16.Digitizer 12 has five output positions which are identified and will bereferred to as Steps I to Step 5, or Output Stages 1 to Output Stage 5.Conductors 18-1 to 18-5 respectively couple Steps 1-5 to Stages l-S sothat each stage monitors a different output stage of digitizer 12.

Each of the stages in ring counter 10 includes a locking circuit whichis responsive to the condition of the associated digitizer step andoperative to lock the stage in the on condition after the stage isturned on" by the advancing ring counter.

Finally, there is provided a reset means 20 which has one of its outputterminals connected to digitizer 12 through conductor 22, and the otherof its output terminals connected to the locking circuit of Stage 1through conductor 24.

The operation of the device shown in FIG, 1 will now be explained. Ringcounter 10 is, except for the locking circuit in each stage, a normallyfree-running ring counter in which one stage is normally on" while allremaining stages are normally off, and in which the on" condition of thestages advances sequentially from one stage to the next. Stage 1 hasbeen arbitrarily selected as the starting stage since reset means 20 isconnected thereto and will turn this stage to the on condition afterreset. Ring counter 10, because of the locking circuit in each stage, isfree-running only as long as the condition of Steps 1-5 is false,indicating the steps at a second potential. As soon as a step changes toa true condition, it energizes the lockup circuit in the stage to whichit is connected, and maintains that stage is the on" condition after thering counter turns it on.

Digitizer 12, which may take the form of a stepping chain, is a meansfor converting an analog input signal applied to it on conductor 12 intoa digital output signal having selected steps. By way of illustration,but not limitation, an example of a digital code is shown in FIG. 2which is suitable of monitoring the amplitude of a voltage, which mayrange anywhere between and volts. The condition being monitored is onein which of five ranges the voltage amplitude is at any time.

FIG. 2 is a truth table for a digitizer having five steps for indicatingthe amplitude of the voltages in five ranges. 1f the applied voltage isbetween 0 and l volt, Step 5 becomes true which is indicated by thenumber 1 in the truth table, and all other steps remain false which isindicated by the number 0 in the truth table. If the applied voltage isbetween 1 and 2 volts, Step 4 becomes true, and Steps 1-3 remains false,the condition of remaining Step 5 being of no importance which isindicated in the truth table. Similarly, each time the applied voltageincreases above 2,3 and 4 volts, the true condition of the steps changesfrom Step 3 to Step 1 as indicated in the truth table.

Assume next that the function being monitored is at a potential whosevoltage is between 1 and 2 volts. According to the truth table, Steps 1,2 and 3 are false, Step 4 is true, and Step 5 is of no consequence.Further assume that this occurs at the instant of time that Stage 1 ofcounter is in the on condition. Since Steps 1, 2 and 3 are false,"counter 10 will advance and sequentially turn on Stage 2, Stage 3 andStage 4. However, since Step 4 is true, indicating that the functionbeing monitored is between 1 and 2 volts, the locking circuit in Stage 4is energized, and Stage 4 will remain on, giving an indication that thefunction being monitored has a voltage in the l to 2-volt range.

Reset means may take the form of a free-running astable multivibratorhaving a frequency which is equal to the desired cyclic repetition ratefor monitoring the function. In operation, reset means 20 provides adisable pulse on lead 22 which disables digitizer 12, and resets thesame so that all steps are false." This releases the locking signalallowing the ring counter to continue its advance. Simultaneously withthe disable pulse, reset means provides a true signal on lead 24 to lockStage 1 and to thereby read the circuit for making a new determinationof the condition of the function being monitored. As soon as reset means20 releases the system, that is, at the end of the disable pulse andtrue pulse, a new cycle starts. For convenience of determining the stagewhich is on," a driver with a light source may be provided.

Referring now to H0. 3, the circuit there shown has been found eminentlysuitable to monitor a function applied to it at input terminology. Theillustrated circuit includes a ring counter 100, having five Stages 101,102, 103, 104 and 105. Stage 101 is comprised of an NPN-Transistor T10forming the main element of the first stage which is coupled to thepreceding Stage 105 through a coupling capacitor C5, and which in turnis coupled to the succeeding Stage 102 through coupling capacitor C1.Transistor T10 is conventionally connected between a B+ supply (28 voltsDC) and ground, the collector being connected to the B+ supply through aresistor R10, and the emitter being connected to ground through aresistor R11. There is also provided a diode D10 which connects theemitter of transistor T10 to the base, the base being in the couplingcircuit from the preceding stage. The time during which Stage 101normally remains "on" is determined by the time constant capacitor C1and resistor R21 in the emitter circuit of the transistor of the nextsucceeding stage.

In order to obtain an indication that a particular stage is on, a driverin the form of PNP-transistor T11 is provided which has an indicatorlamp L1 connected between its emitter and 8+ supply. The base oftransistor T11 is connected to the collector of transistor T10.

Similarly, Stage 102 is comprised of an NPN-transistor T20 forming themain element of the second stage, and a PNP- transistor T21 for drivingan indicator lamp L2. The time during which Stage 102 remains "on" afterhaving been turned on" is determined by the time constant of capacitorC2 and resistor R31 which determines when the next stage will be turnedon." The remaining Stages 103, 104 and 105 are constructed in a similarmanner, each including an NPN-transistor forming the main element. aPNP-transistor transistor for driving a lamp and a coupling circuit of apreselected time constant for turning on the successive stage.

Normally, ring counter is free-running and operates in the followingmanner. Assume that transistor T10 is initially conducting to therebysupply base current to transistor T11 which is connected in emitterfollower configuration to drive indicator lamp L1. When transistor T10is on," its collector is negative and maintains coupling capacitor C1negative. When transistor T10 is turned off," its collector swingspositive and charges coupling capacitor C1 thus turning on" T20.Capacitor C1 will discharge through resistor R21 and, upon beingdischarged, turn off transistor T20 which, in turn, will turn on"transistor T30.

Each stage of ring counter 100 further includes a lockup circuit whichis comprised of a transistor controllable by the collector of the stagetransistor. More particularly, Stage 101 is provided with aPNP-transistor T12 which has its base connected to the collector oftransistor T10 and its collector to the base of transistor T10 through adiode D11 so that, if a positive voltage is applied to the emitter oflockup transistor T12, transistor T10 remains turned on." The signalapplied to the emitter of T12 is also referred to as a locking signal,or a true signal, if it is positive and maintains the associated stagein the on condition.

The operation of the lockup circuit is as follows: Assume initially thatvoltage applied to input terminal 99 is above 3.2 and below 4.0 volts,then transistors T53, T43 and T33 will be turned on" and, in turn, turnon transistors T54, T44 and off," Turning on" transistor T34 applies apositive voltage from the collector across diode D32 to the emitter oftransistor T32. As long as transistor T30 is off," nothing happensbecause the base of transistor T32 is positive. As soon as transistorT30 is turned on" by the ring action, its collector swings negative tothereby turn on" locking transistor T32. This, in turn, swings thecollector of transistor T32 positive to thereby maintain the baseelectrode of transistor T30 positive, and maintains transistor T30 onbiased regardless of the voltage on coupling capacitor C2. In thismanner, Stage 103 of ring counter 100 remains locked up until reset byastable device 120.

There is further provided a digitizer or stepping chain 110 which hasfive output stages or steps identified by reference characters 111, 112,113, 114 and 115. As will become better understood hereinafter, eachstep of stepping chain 110 is connected to a stage of ring counter 100.The connection between Step 111 and Stage 101 is from resistor R14 todiode D12, between Step 112 and Stage 102 is from resistor R24 to diodeD22, between Step 113 and Stage 103 is from resistor R34 to diode D32,between Step 114 and Stage 104 is from resistor R44 to diode D42, andbetween Step 115 to Stage is from resistor R54 to diode D52.

Step 111 of digitizer is comprised of a pair of transistors, such asNPN-transistor T13 and PNP-transistor T14, which are connected in such amanner that when transistor T13 is turned on it turns "on transistorT14. Turning on of transistor T14 generates a true signal on itscollector which is applied, through resistor R14 and diode D12, tolockup circuit transistor T12 of Stage 101 which, as has already beenexplained, locks the ring counter.

More particularly, transistor T13 has its emitter connected to groundthrough four series-connected diodes D13, D14, D15 and D16, and has itsemitter connected to a source of B+ through biasing resistor R12. Thebase of transistor T13 is connected, through a suitable isolation diodeD17, to digitizer input terminal 99, having connected thereto thefunction to be monitored. The base of transistor T14 is connected,through a resistor R13, to the collector of transistor T13 and theemitter of transistor T14 is connected to the source of 8+ which iscontrolled by a switched transistor T63 which, as will be explainedhereinafter, forms part of a reset means 120. Finally, the collector oftransistor T13 is connected through resistor R14, as already mentioned,to the emitter of transistor T12 forming the lockup transistor of Stage101 of ring counter 100.

The operation of Step 111 is as follows-if the function being monitoredby connection to terminal 99 is sufficiently large to turn on steptransistor T13 it, in turn, will turn on output transistor T14 and atrue signal will be applied to lockup circuit transistor T12. Thevoltage necessary to turn on step transistor T13 is readily calculablesince the voltage drop across each diode and across each transistor isapproximately 0.8 volts for current flow. Accordingly, since theconnection between terminal 99 and ground through transistor T13includes five diodes and one transistor, the minimum voltage necessaryis 4.8 volts. 1f the voltage is less than 4.8 volts, transistor T13 willremain turned oft and the signal applied to transistor T12 remainsfalse."

The remaining steps of digitizer 110 are similarly constructed. Stage112 includes a step transistor T23 which has its collector connected toground through three serially connected diodes, D23, D24 and D25, andits emitter connected to the B+ supply through resistor R22. The base oftransistor T23 is connected, through an isolated diode D26, to terminal99. Output transistor T24 has its base connected to the emitter oftransistor T23 through resistor R23, and its collector is connectedthrough a resistor R24 and a diode D22 to the lockup circuit transistorT22 of Stage 102.

The remaining Stages 113, 114 and 115 are constructed similarly toStages 111 and 112 except that each succeeding stage has one less diodein the emitter circuit of its step transistors T33, T43 and T53respectively. Accordingly, a voltage between 1.6 and 2.4 volts isrequired to turn on" transistor T53 to cause lockup of counter Stage105, a voltage between 2.4 and 3.2 volts is required to turn ontransistor T43 to cause lockup of Stage 104, a voltage between 3.2 and4.0 volts is required to turn on" transistor T33 to cause lockup ofStage 103, and a voltage between 4.0 and 4.8 volts is required to turnon" transistor T23 to cause lockup of Stage 102.

There is further provided a reset means 120 which is comprised of a pairof transistors T61 and T62 which are interconnected,,through capacitorsC61 and C62 and resistors R61, R62, R63 and R64, to form a free-runningmultivibrator having a selected frequency. The collector of transistorT61 is also connected, through a diode D60 and a resistor R65, to diodeD12 to cause lockup of Stage 101 when transistor T61 is turned on" whichtakes place once each cycle of the frequency of means 120. The collectorof transistor T62 is connected to the base of the B+ control transistorT63 to remove B+ voltage from the transistors T14, T24, T34, T44 andT54. When transistor T61 in on, transistor T62 is off which, in turn,turns off transistor T63. Since transistor T63 is connected between theB+ supply and the emitters of transistors T14, T24, T34, T44 and T54, aturning 01? of transistor T63 causes transistors T14, T24, T34, T44 andT44 to be without B+ supply, turning all of them off." This releases anylockup stages of ring counter 100, except for the lockup of the firststage provided by the output of transistor T61 during its being turnedon."

Accordingly, when transistor T61 is turned on," reset means 120 releasesall locked-up stages and locks up Stages 101. Reset means 120, by virtueof its connection to transistor T63, has an asymmetrically duty cycle sothat the time during which transistor T61 is fon" is smaller than thetime during which it is off' A suitable duty cycle is a time ratio of1:3 and a suitable cycle frequency is one-twentieth [20second cycleduration with 5 seconds on" time].

The following circuit component values for the circuit illustrated inP10. 3 have been found to give satisfactory operation in the monitoringof a voltage at terminal 99, and the lighting up of lamps L1, L2, L3, L4and L5 when the monitored voltage has the following ranges: 1.0, 1.8,2.6, 3.4 and 4.2

Transistors T10.T20,T30,T40 and T50: 2N2222 (NPN) Transistors TlI,T21,T31,T41 and T51: 2N2907 (PNP) Transistors T12.T22,T32,T42 and T52:2N2907 (PNP) Transistors T13,T23,T33,T43 and T53: 2N2222 (PNP)Transistors T14,T24,T34,T44 and T54: 2N2907 (PNP) Transistors T61 andT62: 2N2222 (NPN) Transistor T63: 2N2222 (N PN) ResistorsR10.R20,R30,R40 and R50: 6.8 kn Resistors Rl1,R2l,R31,R4l and R51: 4.7kn Resistors R12.R22.R32.R42 and R52: 10.0 kn Resistors R13,R23,R33.R43and R53: 10.0 k Resistors R14.R24.R34,R44 and R54: 27.0 It Resistors R62and R63: 100.0 k Resistors R61 and R64: 4.7 k Capacitors Cl,C2,C3,C4 andC5: 10 pf. Capacitors C61 and C62: 1.0 pf. All diodes: 1N4154 There hasbeen described hereinabove a circuit suitable for cyclically monitoringthe condition of a function to continually ascertain the conditionwithin selected ranges. The circuit is simple, reliable and lends itselfideally to applications where assurance is desired that the monitoredfunction is within a selected range.

What is claimed is:

1. A monitoring circuit for indicating the range within which an analogsignal is. located among a plurality of preselected ranges comprising:

digitizer means responsive to said analog signal for deriving a digitalsignal representing the range within which said analog signal is locatedamong said plurality of ranges;

counter means having a plurality of stages, each of said stagesrepresenting one of said plurality of ranges and being operable in afirst and a second condition, said stages being interconnected forswitching from said first to said second condition in sequential orderfrom one stage to another such that only one stage is in said secondcondition at a time; and

locking means associated with said counter means, said locking meansbeing coupled to said digitizer means and responsive to said digitalsignal for locking the stage representing the range within which saidanalog signal is located in the second condition.

2. A monitoring circuit as recited in claim 1 and further includingdisplay means coupled to said counter means for identifying the stage ofsaid'counter means which is locked in the second condition.

3. A circuit for monitoring and indicating the condition of a functioncomprising:

a ring counter including a plurality of stages, each stage beingoperable in a first and a second condition and all stages beinginterconnected such that one and only one stage is in said secondcondition at any time, each stage being associated with a differentcondition of said function;

locking means included in each stage, each of said locking means beingresponsive to a locking signal for locking the stage in said secondcondition during the occurrence of said locking signal; and

means for monitoring said function and for providing a locking signal tothe stage associated with the monitored condition of said function.

4. A circuit in accordance with claim 3 in which said locking means isoperative only on a stage in said second condition and maintains thesame in said second condition.

5. A circuit in accordance with claim 3 in which said means formonitoring said function comprises a digitizer including a plurality ofoutput terminals, said digitizer being responsive to said function andoperative to apply locking signals to selected output terminals toreflect the monitored condition of said function, each output terminalbeing coupled to a different locking means.

6. A circuit in accordance with claim 3 in which said means formonitoring said function comprises a stepping chain having a commoninput tenninal and a different output terminal for each step of saidstepping chain, said function being monitored being connected to saidinput terminal and each of said output terminals being coupled to adifferent locking means.

7. A circuit in accordance with claim 6 in which each output terminal ofsaid stepping chain has a first or a second condition in accordance withthe condition of said function and in which said output terminals arecoupled to said locking means in a preselected manner.

8. A circuit in accordance with claim 3 which further includes a resetmeans coupled to a selected stage of said ring counter and to saidmonitoring means, said reset means being operative to periodically andsimultaneously disable said monitoring means from providing lockingsignals and locking said selected stage in said second condition for apredetermined time interval.

9. A monitoring circuit for deriving an indication of the state of afunction, comprising:

digitizer means responsive to said function for deriving a digitalsignal indicative of the state of said function;

normally free-runningring counter means having a stage for each of saidderivable digital signals, said counter means having only one stage inthe true condition at any time; and

each stage of said counter means including a locking means,

each locking means being connected to said digitizer means for beingresponsive to a different digital signal for maintaining the stage withwhich it is associated in the true condition upon the occurrence of thedigital signal to which it is responsive.

10. A monitoring circuit in accordance with claim 9 in which the lockingmeans of adjacent stages are made responsive to digital signals whichare indicative of adjoining states of said function whereby a change inthe state of said function will lock or release immediately adjacentstages of said ring counter means.

11. A monitoring circuit in accordance with claim 9 which furtherincludes a reset means for providing a cyclically recurring reset pulse,said ring counter means being responsive to said reset pulse andoperative to set a selected stage to said true condition.

12. A monitoring circuit in accordance with claim ll in which saiddigitizer means is responsive to said reset pulse and operative todisable the same from deriving digital signals.

13. A monitoring circuit in accordance with claim 9 in which each stageof said ring counter means includes a stage transistor which is on whenthe stage is in the true condition, and in which said locking circuitincludes a locking transistor which is turned on upon the occurrence ofthe digital signal to which it is responsive, said locking transistorbeing connected to maintain said stage transistor on as long as saidlocking transistor is on.

1. A monitoring circuit for indicating the range within which an analogsignal is located among a plurality of preselected ranges comprising:digitizer means responsive to said analog signal for deriving a digitalsignal representing the range within which said analog signal is locatedamong said plurality of ranges; counter means having a plurality ofstages, each of said stages representing one of said plurality of rangesand being operable in a first and a second condition, said stages beinginterconnected for switching from said first to said second condition insequential order from one stage to another such that only one stage isin said second condition at a time; and locking means associated withsaid counter means, said locking means being coupled to said digitizermeans and responsive to said digital signal for locking the stagerepresenting the range within which said analog signal is located in thesecond condition.
 2. A monitoring circuit as recited in claim 1 andfurther including display means coupled to said counter means foridentifying the stage of said counter means which is locked in thesecond condition.
 3. A circuit for monitoring and indicating thecondition of a function comprising: a ring counter including a pluralityof stages, each stage being operable in a first and a second conditionand all stages being interconnected such that one and only one stage isin said second condition at any time, each stage being associated with adifferent condition of said function; locking means included in eachstage, each of said locking means being responsive to a locking signalfor locking the stage in said second condition during the occurrence ofsaid locking signal; and means for monitoring said function and forproviding a locking signal to the stage associated with the monitoredcondition of said function.
 4. A circuit in accordance with claim 3 inwhich said locking means is operative only on a stage in said secondcondition and maintains the same in said second condition.
 5. A circuitin accordance with claim 3 in which said means for monitoring saidfunction comprises a digitizer including a plurality of outputterminals, said digitizer being responsive to said function andoperative to apply locking signals to selected output terminals toreflect the monitored condition of said function, each output terminalbeing coupled to a different locking means.
 6. A circuit in accordancewith claim 3 in which said means for monitoring said function comprisesa stepping chain having a common input terminal and a different outputterminal for each step of said stepping chain, said function beingmonitored being connected to Said input terminal and each of said outputterminals being coupled to a different locking means.
 7. A circuit inaccordance with claim 6 in which each output terminal of said steppingchain has a first or a second condition in accordance with the conditionof said function and in which said output terminals are coupled to saidlocking means in a preselected manner.
 8. A circuit in accordance withclaim 3 which further includes a reset means coupled to a selected stageof said ring counter and to said monitoring means, said reset meansbeing operative to periodically and simultaneously disable saidmonitoring means from providing locking signals and locking saidselected stage in said second condition for a predetermined timeinterval.
 9. A monitoring circuit for deriving an indication of thestate of a function, comprising: digitizer means responsive to saidfunction for deriving a digital signal indicative of the state of saidfunction; normally free-running ring counter means having a stage foreach of said derivable digital signals, said counter means having onlyone stage in the true condition at any time; and each stage of saidcounter means including a locking means, each locking means beingconnected to said digitizer means for being responsive to a differentdigital signal for maintaining the stage with which it is associated inthe true condition upon the occurrence of the digital signal to which itis responsive.
 10. A monitoring circuit in accordance with claim 9 inwhich the locking means of adjacent stages are made responsive todigital signals which are indicative of adjoining states of saidfunction whereby a change in the state of said function will lock orrelease immediately adjacent stages of said ring counter means.
 11. Amonitoring circuit in accordance with claim 9 which further includes areset means for providing a cyclically recurring reset pulse, said ringcounter means being responsive to said reset pulse and operative to seta selected stage to said true condition.
 12. A monitoring circuit inaccordance with claim 11 in which said digitizer means is responsive tosaid reset pulse and operative to disable the same from deriving digitalsignals.
 13. A monitoring circuit in accordance with claim 9 in whicheach stage of said ring counter means includes a stage transistor whichis on when the stage is in the true condition, and in which said lockingcircuit includes a locking transistor which is turned on upon theoccurrence of the digital signal to which it is responsive, said lockingtransistor being connected to maintain said stage transistor on as longas said locking transistor is on.